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| ? 2015-2016 microchip technology inc. ds20005386b-page 1 pac1710/20 features ? single and dual high-side current sensor - current measurement is integrated over 2.5 ms to 2.6 seconds with up to 11-bit resolution - 1% current measurement accuracy in positive range - measures v source voltages ?calculates power ?v source voltage range 0v to 40v ? bidirectional current sensing ? auto-zero input offset voltage ? digital averaging - adjustable sampling time and resolution ? 5 a typical standby current ? programmable sense voltage range - 10 mv, 20 mv, 40 mv, and 80 mv ? power supply range 3.0v to 5.5v ? wide temperature operating range: -40c to +85c ?alert output for voltage and current out of limit transients between sampling interval ? smbus 2.0 communications interface - block read and block write - address selectable by resistor decode ? sample time configurable from 2.5 ms to 320 ms - with averaging effective sampling times up to 2.6 seconds ? 10-lead 3 x 3 mm vdfn package applications ? notebook and desktop computers ? industrial ? power management systems ? embedded applications ?servers description the pac1710/20 are single and dual high-side bidirectional current sensing monitors with precision voltage measurement capabilities. each sensor measures the voltage developed across an external sense resistor to represent the high-side current of a battery or voltage regulator. the pac1710/20 also measures the sense+ pin voltage and calculates average power over the integration period. the pac1710/20 can be programmed to assert the alert pin when high and low limits are exceeded for current sense and bus voltage. the pac1710/20 device is good for measuring dynamic power. the long integration time allows for extending system polling cycles without losing any power consumption information. in addition the alert ensures that transient events are captured between the polling cycles. available in a rohs compliant 3 x 3 mm 10-pin vdfn package. package types sense2+ ? sense1- sense2- ? smclk smdata 1 2 3 4 10 9 8 7 alert v dd sense1+ ep 11 6 5 addr_sel gnd pac1710/20 3x3 vdfn* *includes exposed thermal pad (ep), see ta b l e 3 - 1 ?pac1720 only. single and dual high-side current-sense monitor with power calculation
pac1710/20 ds20005386b-page 2 ? 2015-2016 microchip technology inc. device block diagram smbus interface smclk smdata addr_sel sense2+ sense2- voltage registers configuration current registers current limits voltage limits alert power register current measurement voltage measurement power management v dd gnd configuration current measurement voltage measurement sense1+ sense1- analog mux pac1720 only ? 2015-2016 microchip technology inc. ds20005386b-page 3 pac1710/20 1.0 electrical characteristics 1.1 electrical specifications absolute maximum ratings (?) v dd pin........................................................................................................................... .................................-0.3 to 6.0v voltage on sense- and sense+ pins.............................................................................................. ...............-42 to 42v voltage on any other pin to gnd ................................................................................................ ..-gnd-0.3 to v dd +0.3v voltage between sense pins (|(sense+ ? sense-)|)................................................................................................40v input current to any pin except v dd ......................................................................................................................+10 ma output short-circuit current................................................................................................... ........................... continuous package power dissipation ( note ) ............................................................................................ 0.5w up to t a = 85c/w junction to ambient ( ? j-a ) .............................................................................................................................. .......78c/w operating ambient temperature range ............................................................................................ ............. -40 to 85c storage temperature range...................................................................................................... ................... -55 to 150c esd rating ? smclk, smdata, and alert pins ? hbm.....................................................................................8000v sd rating ? all other pins ? hbm........................................................................................................................... . 2000v ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended peri- ods may affect device reliability. note: the package power dissipation specification assumes a recommended thermal via design consisting of a 2 x 3 matrix of 0.3 mm (12 mil) vias at 0.9 mm pitch connected to the ground plane with a 1.6 mm x 2.3 mm thermal landing. pac1710/20 ds20005386b-page 4 ? 2015-2016 microchip technology inc. table 1-1: dc characteristics electrical characteristics : unless otherwise specified, maximum values are at t a = -40c to +85c, v dd = 3v to 5.5v, v source = 0v to 40v; typical values are at t a = +25c, v dd = 3.3v, v source = 24v, v sense = (sense+ ? sense-) = 0v; current sense full scale range = 80 mv unless otherwise noted characteristic symbol min. typ. max. unit conditions power supply voltage on sense+ v source 0?40v v dd range v dd 3.0 ? 5.5 v v dd pin supply current (pac1720) i dd ? 0.525 1.3 ma both measurement channels enabled. continuous conversions (see ta b l e 4 - 1 ) ? 13 50 a both measurement channels enabled. one conversion per second (see table 4-1 ). vsrc_samp_time = 2.5 ms cs_samp_time = 2.5 ms no smbus communications v dd pin supply current (pac1710) i dd ? 360 900 a continuous conversions (see ta b l e 4 - 1 ) ? 10 35 a one conversion per second (see ta b l e 4 - 1 ). vsrc_samp_time = 2.5 ms cs_samp_time = 2.5 ms no smbus communications v dd rise rate v dd_rise 0.03 v/ms 0 to 3v in 100 ms v dd standby current i dd_stby ? 5.5 15 a standby state analog input characteristics sense+/sense- pins common-mode voltage range v cm 0 ? 40 v common-mode voltage on sense pins, referenced to ground v sense differential input voltage range v diff -80 ? +80 mv voltage between sense+ and sense- pins current-sense power supply rejection ratio psrr_cs ? 10 ? v/v 3.0v < v dd < 5.5v full-scale range () (see section 4.4 ?current measurement? ) fsr -10 ? 10 mv 1 lsb = 4.885 v 11-bit data resolution -20 ? 20 mv 1 lsb = 9.77 v 11-bit data resolution -40 ? 40 mv 1 lsb = 19.54 v 11-bit data resolution -80 ? 80 mv 1 lsb = 39.08 v 11-bit data resolution common-mode rejection v sense _cmrr 80 100 ? db common-mode rejection, 0v < v source < 40v sense+/sense- pins common-mode voltage range v cm 0 ? 40 v common-mode voltage on sense pins, referenced to ground v bus gain accuracy v bus_gain_err ? ? 0.4 % measured at adc output, gain = 1 ? 2015-2016 microchip technology inc. ds20005386b-page 5 pac1710/20 sense+, sense- pin leakage current i sense +, i sense- ??1.0av bus = 24v, v sense = 0v sleep state sense+, sense- pin leakage current i sense +, i sense- ??1.0av dd = 0v sense+ pin bias current i sense + ? 100 150 a -80 mv < v sense < 80 mv active state sense- pin bias current i sense- ?0.11a-80mv < v sense < 80 mv active state current-sense offset error voltage offset error voltage (referred to input) v os ?15?vfsr = 10mv ?15?vfsr = 20mv ?20?vfsr = 40mv ?40?vfsr = 80mv current-sense total measurement error total error (positive range) (see section 4.4 ?current measurement? ) v sense _tot_err ?0.51% fsr fsr = 0 to +10 mv ?0.30.6% fsr fsr = 0 to +20 mv ?0.20.4% fsr fsr = 0 to +40 mv ?0.20.4% fsr fsr = 0 to +80 mv total error (negative range) (see section 4.4 ?current measurement? ) v sense _tot_err -1 -1.3 -1.6 % fsr fsr = -10 mv to 0 -1 -1.3 -1.6 % fsr fsr = -20 mv to 0 -1 -1.3 -1.6 % fsr fsr = -40 mv to 0 -1.6 -2 -2.4 % fsr fsr = -80 mv to 0 v source voltage measurement power supply rejection ratio psrr ? 10 ? mv/v 3.0v < v dd < 5.5v v source error () v source_ err ?0.150.3% fsv table 1-1: dc characteristics (continued) electrical characteristics : unless otherwise specified, maximum values are at t a = -40c to +85c, v dd = 3v to 5.5v, v source = 0v to 40v; typical values are at t a = +25c, v dd = 3.3v, v source = 24v, v sense = (sense+ ? sense-) = 0v; current sense full scale range = 80 mv unless otherwise noted characteristic symbol min. typ. max. unit conditions pac1710/20 ds20005386b-page 6 ? 2015-2016 microchip technology inc. power ratio total power ratio measurement error () (positive range) p ratio _err ??1% fsr fsr = 0 to +10 mv, 0 to +20 mv, 0 to +40 mv, or 0 to +80 mv total power ratio measurement error () (negative range) p ratio _err ??2% fsr fsr = -10 mv to 0, -20 mv to 0, -40 mv to 0, or -80 mv to 0 first power ratio ready t conv_p ? ? 220 ms time after power-up before p ratio updated digital i/o pins (smclk, smdata, alert ) pull-up voltage range v pullup 3.0 ? 5.5 v pull-up voltage for smbus and alert pins time to first communications t comm ??25ms input high voltage v ih 2.0 ? ? v smclk, smdata od pins pulled up to v pullup input low voltage v il ??0.8v output low voltage v ol ? ? 0.4 v od pin pulled to v pullup 3 ma current sink leakage current () i leak ? ? 5 a powered or unpowered t a < +85c table 1-1: dc characteristics (continued) electrical characteristics : unless otherwise specified, maximum values are at t a = -40c to +85c, v dd = 3v to 5.5v, v source = 0v to 40v; typical values are at t a = +25c, v dd = 3.3v, v source = 24v, v sense = (sense+ ? sense-) = 0v; current sense full scale range = 80 mv unless otherwise noted characteristic symbol min. typ. max. unit conditions ? 2015-2016 microchip technology inc. ds20005386b-page 7 pac1710/20 figure 1-1: smbus timing. table 1-2: smbus module specifications electrical characteristics : unless otherwise specified, maximum values are at t a = -40c to +85c, v dd = 3v to 5.5v, v bus = 0v to 32v; typical values are at t a = +25c, v dd = 3.3v, v bus = 24v, v sense = (sense+ ? sense-) = 0v characteristic sym. min. typ. max. units conditions smbus interface input capacitance c in ? 4 10 pf smbus timing clock frequency f smb 10 ? 400 khz spike suppression t sp ? ? 100 ns bus free time stop to start t buf 1.3 ? ? s start setup time t su:sta 0.6 ? ? s start hold time t hd:sta 0.6 ? ? s stop setup time t su:sto 0.6 ? ? s data hold time t hd:dat 0 ? ? s when transmitting to the master data hold time t hd:dat 0.3 ? ? s when receiving from the master data setup time t su:dat 0.6 ? ? s clock low period t low 1.3 ? ? s clock high period t high 0.6 ? ? s clock/data fall time t fall ? ? 300 ns min = 20 + 0.1 c load ns clock/data rise time t rise ? ? 300 ns min = 20 + 0.1 c load ns capacitive load c load ? ? 400 pf total per bus line smdata smclk t low t rise t high t fall t buf t hd:sta p s s - start condition p - stop condition t hd:dat t su:da t t su:sta t hd:sta p t su:sto s pac1710/20 ds20005386b-page 8 ? 2015-2016 microchip technology inc. notes: ? 2015-2016 microchip technology inc. ds20005386b-page 9 pac1710/20 2.0 typical operating curves note: unless otherwise indicated, maximum values are at t a = -40c to +85c, v dd = 3v to 5.5v, v source = 0v to 40v; typical values are at t a = +25c, v dd = 3.3v, v source = 24v, v sense = (sense+ ? sense-) = 0v. figure 2-1: i dd vs. v dd , continuous conversions ( pac1710 ). figure 2-2: i dd vs. v dd , one conversion per second, lowest resolution ( pac1710 ). figure 2-3: i dd vs. v dd , standby mode ( pac1710) figure 2-4: i sense + pin current vs. v bus (t a = -40c to +85c). figure 2-5: i sense + pin bias current (80 mv range). figure 2-6: i sense - pin bias current (80 mv range, t a = -40c to +85c). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes onl y. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 320.0 340.0 360.0 380.0 400.0 420.0 440.0 3.0 3.3 3.6 4.5 5.0 5.5 i dd ( a) v dd (v) t = +85?c t = +25?c t = - 40?c 8.0 10.0 12.0 14.0 16.0 18.0 20.0 3.0 3.3 3.6 4.5 5.0 5.5 i dd ( a) v dd (v) t = +85 c t = +25 c t = - 40?c 3.000 4.000 5.000 6.000 7.000 8.000 9.000 10.000 11.000 12.000 13.000 3.0 3.3 3.6 4.5 5.0 5.5 i dd ( a) v dd (v) t = +85?c t = +25?c t = - 40?c -20.000 0.000 20.000 40.000 60.000 80.000 100.000 120.000 0 10203040 50 i sense + current ( a) v bus (v) 97.5 98.0 98.5 99.0 99.5 100.0 100.5 101.0 101.5 102.0 i sense + current ( a) v sense (% of full scale) t = +85 c t = +25 c t = - 40?c -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 i sense - current ( a) v sense (% of full scale) pac1710/20 ds20005386b-page 10 ? 2015-2016 microchip technology inc. figure 2-7: i dd vs. v dd , continuous conversions ( pac1720 ). figure 2-8: i dd vs. v dd , one conversion per second, lowest resolution ( pac1720). figure 2-9: i dd vs. v dd , standby mode ( pac1720). figure 2-10: i sense + pin leakage current, t a = -40c to +85c. figure 2-11: i sense - pin leakage current, t a = -40c to +85c. 460.0 480.0 500.0 520.0 540.0 560.0 580.0 600.0 3.0 3.3 3.6 4.5 5.0 5.5 i dd ( a) v dd (v) t = +85?c t = +25?c t = - 40?c 10.000 12.000 14.000 16.000 18.000 20.000 22.000 3.0 3.3 3.6 4.5 5.0 5.5 i dd ( a) v dd (v) t = +85?c t = +25?c t = - 40?c 000 4000 5000 000 000 8000 000 0000 000 2000 000 0 45 50 55 a) v dd (v) t = +85?c t = +25 c t = - 40?c -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 i sense + current [ a] v sense (% of full scale) -0.020 -0.015 -0.010 -0.005 0.000 0.005 0.010 i sense + current ( a) v sense (% of full scale) ? 2015-2016 microchip technology inc. ds20005386b-page 11 pac1710/20 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . 3.1 sense1+/sense1- these two pins form the differential input for measuring voltage across a sense resistor in the application. the positive input (sense1+) also acts as the input pin for bus voltage. 3.2 sense2+/sense2- (pac1720 only) these two pins form the differential input for measuring voltage across a sense resistor in the application. the positive input (sense2 +) also acts as the input pin for bus voltage. 3.3 ground (gnd) system ground. 3.4 address selection (addr_sel) address selection for the smbus slave address, based on the pull-down resistor. 3.5 smbus alert ( a lert ) this pin is the smbus alert pin that is asserted under fault conditions. 3.6 smbus data (smdata) this is the bidirectional smbus data pin. this pin is open drain, and requires a pull-up resistor. 3.7 smbus clock (smclk) this is the smbus clock pin. this pin is open drain, and requires a pull-up resistor. 3.8 positive power supply voltage (v dd ) power supply input pin for the device. 3.9 exposed thermal pad (ep) this pad should be connected to ground for noise immunity. table 3-1: pin descriptions pac1710/20 3x3 vdfn symbol type (see table 3-2 ) description 1 sense1+ aio40 vbus1/vsense1+ input 2 sense1- aio40 vsense1- input 3 sense2+ aio40 vbus2/vsense2+ input 4 sense2- aio40 vsense2- input 5 gnd power ground 6 addr_sel aio selects smbus/i 2 c? address 7alert do smbus alert pin 8 smdata diod smdata: smbus - requires pull-up resistor 9 smclk di smclk: smbus - requires pull-up resistor 10 v dd power positive power supply voltage 11 ep ? not internally connected, but recommend grounding. table 3-2: pin types description pin type description power this pin is used to power the device aio40 analog input/output ? this pin is used as an i/o for analog signals. maximum voltage is 40v. aio5 analog input/output ? this pin is used as an i/o for analog signals. maximum voltage is 5v. di digital input ? this pin is used for digital inputs diod digital input/output open drain ? this pin is used for digital i/o and is open drain pac1710/20 ds20005386b-page 12 ? 2015-2016 microchip technology inc. notes: ? 2015-2016 microchip technology inc. ds20005386b-page 13 pac1710/20 4.0 general description the pac1710/20 is a bidirectional high-side current-sensing device with precision voltage measurement capabilities. it measures the voltage developed across an external sense resistor to represent the high-side current of a battery or voltage regulator. the pac1710/20 also measures the sense1+ and sense2+ pin voltages (v source ) and calculates average power over the integration period. the pac1710/20 measures the differential voltage across an external sense resistor, digitizes it with a variable resolution (6-bit to 11-bit plus sign) sigma-delta adc, and transmits via the smbus or the i 2 c? protocol. the current range allows for large variations in measured current with high accuracy and low voltage drop across the resistor. the pac1710/20 has programmable high and low limits for current sense and bus voltage with a maskable alert signal to the host when an out-of-limit measurement occurs. a system diagram is shown in figure 4-1 . figure 4-1: pac1710/20 system diagram. pac1710/20 host mcu smdata smclk alert v source 0v C 40v sense resistors v dd sense2- sense2+* 3.0v to 5.5v addr_sel gnd 3.0v to 5.0v sense1+ sense1- * 100k C 1m 5.2v zener note 1: the device must be biased prior to applying v source . failure to do so will result in damage. 2: the unpowered bias on v dd must be greater than v dd , if v dd will be removed prior to v source . * pac1720 only. pac1710/20 ds20005386b-page 14 ? 2015-2016 microchip technology inc. 4.1 power states the pac1710/20 has three states of operation: ?active ? the pac1710/20 initiates conversion cycles for the programmed conversion rate. ? standby ? this is the lowest power state. there are no conversion cycles. the majority of circuitry is powered-down to reduce supply current to a minimum. the smbus is active and the part will return requested data. to enter the standby state, disable all measurements (see register 6-1 ). ? one-shot ? while the device is in the standby state, the host can initiate a conversion cycle on demand (see register 6-3 ). after the conversion cycle is complete, the device will return to the standby state. 4.2 conversion cycle the conversion cycle is the period of time in which the measurements are taken and the data is updated. in the active state, individual measurement can be disabled. in the standby state, all measurements are updated. during the conversion cycle, both channels on the pac1720 begin taking measurements at the same time. in both devices, the v sense sample is taken first for its programmed sample time. then, the v source sample is taken for its programmed sample time. digital averaging may be applied to average the last 2-8 samples. sample time and digital averaging have separate controls for v sense and v source as well as for each channel, in the case of pac1720. (see register 6-7 and register 6-8 ). at the end of the conversion cycle, the enabled measurements are updated. the power ratio, high limit status (which includes a conv_done status bit), and low limit status registers are always updated. the alert pin will be asserted, by default, if any out-of-limit conditions exist (see section 4.7 ?alert output? ). 4.3 conversion rate for power management in the active state, a conversion rate can be programmed. conversion rate specifies how often measurement data should be updated. once per second is the lowest setting (see register 6-2 ). if the actual sampling time for both measurements (v source and v sense ) is greater than 1/conversion rate for either channel, the pac1710/20 will override the programmed conversion rate and operate in continuous mode. 4.4 current measurement the pac1710/20 includes one or two high-side current sensing circuits. these circuits measure the voltage (v sense ) induced across a fixed external current sense resistor (r sense ) and stores the voltage as a signed 11-bit (by default) number in the sense voltage registers. the pac1710/20 current sensing operates in one of four bipolar full-scale ranges (fsr): 10 mv, 20 mv, 40 mv, or 80 mv (see section 4.4 ?current measurement? ). the default fsr is 80 mv. full-scale current (fsc) can be calculated from equation 4-1 . equation 4-1: full-scale current the actual current through r sense can then be calculated using equation 4-2 . equation 4-2: bus current as an example, suppose the system is drawing 1.65a through a 10 m ? resistor, the fsr is set for 20 mv, and sample time is 80 ms. using equation 4-1 , the fsc is 2a. the measured v sense is 1.65a ? 10 m ? = 16.5 mv. this value of v sense is represented in the sense voltage registers as 69_8h ( 0110_1001_1000b or 1688d) ignoring the 4 lower bits of the low byte as these are always 0. this value, when applied to equation 4-2 , results in an i bus current of 1.649a. fsc fsr r sense ---------------------- = where: fsc = full-scale current fsr = 10mv, 20mv, 40mv, or 80mv (see tab l e 4 - 6 ) r sense = external sense resistor value i bus fsc v sense denominator ----------------------------------- ? = where: i bus = actual bus current fsc = full-scale current value (from equation 4-1 ) v sense = the value read from the sense voltage registers (in decimal), ignoring the four lowest bits which are always zero (see register 6-10 and register 6-11 for pac1720) denominator = determined by the sample time, as shown in table 4-5 . ? 2015-2016 microchip technology inc. ds20005386b-page 15 pac1710/20 for a negative voltage, the sense voltage registers are read as 96_0h (again ignoring the lower 4 bits of the low byte as these are always 0). to calculate current, the binary value is first converted from two?s complement by inverting the bits and adding one: 96_80h = 1001_0110_1000b . inverting equals 0110_1001_0111b (69_7h) and adding one gives 0110_1001_1000b (69_8h). this results in the same calculated value as in the positive voltage case. 4.5 voltage measurement the pin voltage is measured on the supply side of the appropriate sense+ pin and stored as an unsigned 11-bit number in the v source voltage registers as v source (see register 6-12 ). full-scale voltage (fsv) is given by the maximum value of the v sense voltage registers: equation 4-3: full-scale voltage actual voltage at sense+ can be calculated using equation 4-4 . equation 4-4: bus voltage as an example using 10-bit resolution, suppose that the actual pin voltage is 24v. the v source voltage registers will report a value of 99_80h ( 1001_1001_10xx_xxxxb ) in 10-bit resolution (default). when reading the data, the lower 5 bits are always ignored. because the default operation is to measure the v source voltage with 10-bit resolution, the sixth bit is likewise ignored. therefore, decoding the upper 10 bits results in a decimal value of 614. this value, when applied in equation 4-3 , results in v source_pin equal to 23.98v. as an example using 11-bit resolution, suppose that the actual pin voltage is 10.65v. the v source voltage registers will report a value of 44_10h ( 0100_0100_001x_xxxxb ). because the lower 5 bits are ignored, the decimal result is 545d. this value, when applied in equation 4-4 , results in v source_pin equal to 10.64v. the v source voltage may also be determined by scaling each bit set by the indicated bit weighting as described in section 4.11 ?vsource data representation? . 4.6 power calculation the pac1710/20 may be used to determine the average power provided at the source side of sense+ (sense1+ and sense2+) using the value p ratio , contained in the power ratio registers (see register 6-14 ). the value represents the percentage of maximum calculable power. p ratio is mathematically generated by multiplying the absolute values of v sense and v source (see section 4.4 ?current measurement? and section 4.5 ?voltage measurement? ) and is stored as a 16-bit number. p ratio is updated whenever either v sense or v source is updated. full-scale power can be calculated from equation 4-5 . equation 4-5: full-scale power fsv 40 40 denominator ----------------------------------- ? = where: fsv = full scale voltage denominator = determined by the sample time, as shown in tab le 4 - 2 v source_pin fsv v source denominator ----------------------------------- ? = where: v source_pin = the actual voltage on the sense1+/sense2+ pin fsv = the full-scale voltage (from equation 4-3 ) v source = the value read from the v source voltage registers (in decimal), ignoring the lowest five bits which are always zero (see section 4.11 ?vsource data representation? ). denominator = determined by the sample time, as shown in tab le 4 - 2 fsp fsc fsv ? = where: fsp = the full-scale power fsc = the full-scale current (from equation 4-1 ) fsv = the full-scale voltage (from equation 4-3 ) pac1710/20 ds20005386b-page 16 ? 2015-2016 microchip technology inc. actual power drawn from the source can be calculated using equation 4-6 . equation 4-6: bus power as an example, suppose that the actual pin voltage is 10.65v, the current through a 10 m ? resistor is 1.65a, the fsr is set for 20 mv, and the sample times are the defaults. the fsc value is 2a per equation 4-1 . the fsv value is 39.96v per equation 4-4 . using equation 4-5 , the fsp value is 79.92w. applying p = v ?? i, the expected power is 17.57w which is 21.98% of the fsp value. reading the power ratio registers will report p ratio as 38_47h ( 0011_1000_0100_0111b or 14,407d). using equation 4-6 , this value results in a calculated bus power of 17.57w which is ~21.98% of the fsp value. 4.7 alert output the alert pin is an open-drain output and requires a pull-up resistor to v pullup. the alert pin is used as an interrupt signal or as an smbus alert signal that allows an smbus slave to communicate an error condition to the master. one or more smbus alert outputs can be hardwired together. the alert pin will be asserted (by default) if the mea- sured v source voltage or v sense voltage are out of limit ( high limit or < low limit). the alert pin will remain asserted as long as an out-of-limit condition remains. once the out-of-limit condition has been removed, the alert pin will remain asserted until the appropriate status bits are cleared. the alert pin can be masked for all out-of-limit measurements by setting the mask_all bit (see register 6-1 ) or for an individual out-of-limit measurement (see register 6-5 ). once the alert pin has been masked, it will be de-asserted if no unmasked out-of-limit conditions exist. any interrupt conditions that occur while the alert pin is masked will update the status registers normally. the alert pin can be asserted for 5 s when all measurements are finished (if enabled by setting conv_done_en, see register 6-1 ). 4.8 conversion rate the conversion rate controls how often v sense , v source , p ratio and the status bits are updated in the active state (see tab l e 4 - 1 ). the conversion rate should only be updated when the pac1710/20 is in the standby state. to do this, disable the measurements in the configuration register 00h, wait for the conversion cycle to complete by monitoring the xmeas_dis bits in 00h until they stay set to ? 1 ?, change the conversion rate, and then enable the desired measurements. 4.9 sampling time and resolution the pac1710/20 sampling interval and resolution for measuring v source and v sense are register controlled. the v source settings based on register values are shown in tab l e 4 - 2 and ta b l e 4 - 3 . the v sense measurements have an additional parameter: full-scale resolution of the differential input. the v sense settings based on register values are shown in table 4-4 , ta b l e 4 - 5 and tab l e 4 - 6 . p bus fsp p ratio 65 535 ? --------------------- - ? = where: p bus = the actual power provided by the source measured at sense+ fsp = the full-scale power (from equation 4-5 ) p ratio = the value read from the power ratio registers (in decimal). see register 6-14 and register 6-15 table 4-1: conversion rate for measurement conv_rate<2:0> conversion rate 10 00 1 per sec 01 2 per sec 10 4 per sec 11 continuous (default) table 4-2: voltage source sampling time settings vsrc_samp_time v source sample time equation 4-3 denominator equation 4-4 denominator 00 2.5 ms (data = 8 bits) 256 255 01 5 ms (data = 9 bits) 512 511 10 10 ms (data = 10 bits) (default) 1024 1023 11 20 ms (data = 11 bits) 2048 2047 table 4-3: voltage source averaging settings vsrc_avg samples to average 00 disabled (default) 01 2 10 4 11 8 ? 2015-2016 microchip technology inc. ds20005386b-page 17 pac1710/20 4.10 sense voltage measurement resolution the sense voltage registers store the measured v sense value (see section 4.4 ?current measurement? ). note that the bit weighting values are for representation of the voltage relative to full scale. there is no internal scaling of data and all normal binary bit weightings still apply. the sense voltage registers data format is standard two?s complement format with the positive full-scale value (7f_fh) and negative full-scale value (80_0h) equal to the programmed fsr. the sign bit indicates the direction of current flow. if the sign bit is ? 0 ?, the current is flowing through r sense from the sense+ pin to the sense- pin. if the sign bit is ? 1 ?, the current is flowing through r sense from the sense- pin to the sense+ pin. data resolution is dependent upon sampling time as shown in table 4-8 . the data format (assuming 11-bit resolution) is shown in tab l e 4 - 7 . this data will scale directly with the sampling time. table 4-4: current-sensing averaging settings cs_samp_avg<1:0> samples to average 00 disabled (default) 01 2 10 4 11 8 table 4-5: current-sensing sampling time settings cs_samp_time<2:0> current sensor sample time equation 4-2 denominator 000 2.5 ms (data = sign + 6 bits) 63 001 5 ms (data = sign + 7 bits) 127 010 10 ms (data = sign + 8 bits) 255 011 20 ms (data = sign + 9 bits) 511 100 40 ms (data = sign + 10 bits) 1023 101 80 ms (data = sign + 11 bits) (default) 2047 110 160 ms (data = sign + 11 bits) 2047 111 320 ms (data = sign + 11 bits) 2047 note 1: 160 ms sampling time has built-in 2x analog oversampling using adc at 12-bit resolution. 2: 320 mx sampling time has built-in 4x analog oversampling using adc at 13-bit resolution. table 4-6: current-sensing range settings cs_rng<1:0> full scale range 00 -10 mv to 10 mv 01 -20 mv to 20 mv 10 -40 mv to 40 mv 11 -80 mv to 80 mv (default) table 4-7: v sense data format v sense binary hex (as read by registers) - full-scale 1000_0000_0000 80_0h -2 lsb 1111_1111_1110 ff_eh -1 lsb 1111_1111_1111 ff_fh 0 0000_0000_0000 00_0h +1 lsb 0000_0000_0001 00_1h +2 lsb 0000_0000_0010 00_2h +full-scale -1 lsb 0111_1111_1111 7f_fh table 4-8: v sense data resolution sampling time resolution () 10 mv 20 mv 40 mv 80 mv 2.5 ms 156.3 v 312.5 v 625.0 v 1.250 mv 5 ms 78.13 v 156.3 v 312.5 v 625.0 v 10 ms 39.06 v 78.13 v 156.3 v 312.5 v 20 ms 19.53 v 39.06 v 78.13 v 156.3 v 40 ms 9.76 v 19.53 v 39.06 v 78.13 v 80 ms 4.88 v 9.76 v 19.53 v 39.06 v pac1710/20 ds20005386b-page 18 ? 2015-2016 microchip technology inc. 4.11 v source data representation the v source voltage registers store the measured v source value (see section 4.5 ?voltage measurement? ). the measured voltage is determined by summing the bit weights of each bit set. for example, if v source was 7.4v, the v source voltage registers would read 0010_1111 for the high byte and 0100_0000b for the low byte corresponding to 5v + 1.25v + 0.625v + 0.3125v + 0.1563v + 0.0390v = 7.3828v. the bit weightings are assigned for human interpretation. they should be disregarded when translating the information via a computing system, as shown in section 4.5 ?voltage measurement? . the v source voltage registers cannot support negative values, so all values less than 0v will be recorded as 0v. 4.12 power ratio data representation the power ratio registers store a power factor value, p ratio , that is used to determine the final average power delivered to the system (see section 4.6 ?power calculation? ). p ratio is the result of the multiplication of the v sense reading and the v source reading values shifted to a 16-bit number. it represents the ratio of delivered power with respect to maximum power. 4.13 limit registers these registers are used in concordance with the alert pin to indicate when high or low limits have been exceeded. 4.13.1 v sense limits the v sense limit registers store a high and low limit for v sense . v sense is compared against both limits after each conversion cycle. the data format for the limit is a raw binary form that is relative to the maximum v sense that has been programmed. if the measured sense voltage meets or exceeds the high limit or drops below the low limit, the alert pin is asserted (by default, see section 4.7 ?alert output? ) and the vsense_high or vsense_low status bits are set in the high limit status or low limit status registers (see register 6-16 and register 6-18 ). 4.13.2 v source limits the v source voltage limit registers store the high and low limits for v source . v source is compared against both limits after each conversion cycle. if v source meets or exceeds the corresponding high limit or drops below the low limit, the alert pin is asserted (by default, see section 4.7 ?alert output? ) and the vsrc_high or vsrc_low status bits are set in the high limit status or low limit status registers (see register 6-20 and register 6-22 ). ? 2015-2016 microchip technology inc. ds20005386b-page 19 pac1710/20 5.0 smbus communication 5.0.1 smbus start bit the smbus start bit is defined as a transition of the smbus data line from a logic ? 1 ? state to a logic ? 0 ? state while the smbus clock line is in a logic ? 1 ? state. 5.0.2 smbus address and rd/w r bit the smbus address byte consists of the 7-bit client address followed by a 1-bit rd/wr indicator. if this rd/wr bit is a logic ? 0 ?, the smbus host is writing data to the client device. if this rd/wr bit is a logic ? 1 ?, the smbus host is reading data from the client device. the pac1710/20 smbus address is determined by a single resistor connected between ground and the addr_sel pin as shown in table 5-1 . all smbus data bytes are sent most significant bit first and composed of 8 bits of information. 5.0.3 smbus ack and nack bits the smbus client will acknowledge all data bytes that it receives (as well as the client address if it matches and the ara address if the alert pin is asserted). this is done by the client device pulling the smbus data line low after the eigth bit of each byte that is transmitted. the host will not acknowledge (nack) the data received from the client by holding the smbus data line high after the eigth data bit has been sent. 5.0.4 smbus stop bit the smbus stop bit is defined as a transition of the smbus data line from a logic ? 0 ? state to a logic ? 1 ? state while the smbus clock line is in a logic ? 1 ? state. when the pac1710/20 detects an smbus stop bit, and it has been communicating with the smbus protocol, it will reset its client interface and prepare to receive further communications. 5.0.5 smbus timeout the pac1710/20 includes an smbus timeout feature. following a 30 ms period of inactivity on the smbus, the device will time out and reset the smbus interface. the time-out functionality defaults to disabled and can be enabled by writing to the timeout bit (see register 6-1 ). 5.1 smbus and i 2 c compliance the major differences between smbus and i 2 c devices are highlighted below. for more information, refer to the smbus 2.0 and i 2 c specifications. ? pac1710/20 supports i 2 c fast mode at 400 khz. this covers the smbus maximum time of 100 khz. ? minimum frequency for smbus communications is 10 khz. ? the smbus client protocol will reset if the clock is held at a logic ? 0 ? for longer than 30 ms. this time- out functionality is disabled by default in the pac1710/20 and can be enabled by writing to the timeout bit. i 2 c does not have a timeout. ? the smbus client protocol will reset if both the clock and data lines are held at a logic ? 1 ? for longer than 200 s (idle condition). this function is disabled by default in the pac1710/20 and can be enabled by setting the timeout bit. i 2 c does not have an idle condition. ?i 2 c devices do not support the alert response address functionality (which is optional for smbus). ?i 2 c devices support block read and block write differently. i 2 c protocol allows for unlimited number of bytes to be sent in either direction. the smbus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. the pac1710/20 supports i 2 c formatting only. table 5-1: addr_sel resistor setting res (5%) smbus address res (5%) smbus address 0 1001_100(r/w) 1600 0101_000(r/w) 100 1001_101(r/w) 2000 0101_001(r/w) 180 1001_110(r/w) 2700 0101_010(r/w) 300 1001_111(r/w) 3600 0101_011(r/w) 430 1001_000(r/w) 5600 0101_100(r/w) 560 1001_001(r/w) 9100 0101_101(r/w) 750 1001_010(r/w) 20000 0101_110(r/w) 1270 1001_011(r/w) open 0011_000(r/w) pac1710/20 ds20005386b-page 20 ? 2015-2016 microchip technology inc. 5.2 smbus protocols the pac1710/20 communicates with a host controller through the smbus. the smbus is a two-wire serial communication protocol between a computer host and its peripheral devices. a detailed timing diagram is shown in figure 1-1 . stretching of the smclk signal is supported; however, the pac1710/20 will not stretch the clock signal. all of the below protocols use the convention in table 5-2 . 5.2.1 write byte the write byte is used to write one byte of data to the registers, as shown in table 5-3 . 5.2.2 read byte the read byte protocol is used to read one byte of data from the registers as shown in ta b l e 5 - 4 . 5.2.3 send byte the send byte protocol is used to set the internal address register pointer to the correct address location. no data is transferred during the send byte protocol as shown in tab l e 5 - 5 . 5.2.4 receive byte the receive byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via send byte). this is used for consecutive reads of the same register as shown in ta b l e 5 - 6 . table 5-2: protocol format data sent to device data sent to the host # of bits sent # of bits sent table 5-3: write byte protocol start slave address wr ack register address ack register data ack stop 1 ? 0 yyyy_yyy 0 0 xxh 0 xxh 0 0 ? 1 table 5-4: read byte protocol start slave address wr ack register address ack start slave address rd ack register data nack stop 1 ? 0 yyyy_yyy 0 0 xxh 0 1 ? 0 yyyy_yyy 1 0 xxh 1 0 ? 1 table 5-5: send byte protocol start slave address wr ack register address ack stop 1 ? 0 yyyy_yyy 0 0 xxh 0 0 ? 1 table 5-6: receive byte protocol start slave address rd ack register address nack stop 1 ? 0 yyyy_yyy 1 0 xxh 1 0 ? 1 ? 2015-2016 microchip technology inc. ds20005386b-page 21 pac1710/20 5.2.5 alert response address the alert output can be used as a processor interrupt or as an smbus alert when configured to operate as an interrupt. when it detects that the alert pin is asserted, the host will send the alert response address (ara) to the general address of 0001_100xb . all devices with active interrupts will respond with their client address, as shown in tab le 5 -7 . the pac1710/20 will respond to the ara in the following way if the alert pin is asserted: ? send slave address and verify that full slave address was sent (i.e. the smbus communication from the device was not prematurely stopped due to a bus contention event). ? set the mask bit to clear the alert pin. 5.3 i 2 c protocols the pac1710/20 supports i 2 c block read and block write. the protocols listed below use the convention in table 5-1 . 5.3.1 block write the block write is used to write multiple data bytes to a group of contiguous registers, as shown in table 5-8 . table 5-7: alert response address protocol start alert response address rd ack device address nack stop 1 ? 0 0001_100 1 0 yyyy_yyy 1 0 ? 1 table 5-8: block write protocol start slave address wr ack register address ack register data ack 1 ?? 0 yyyy_yyy 0 0 xxh 0 xxh 0 register data ack register data ack register address register data ack stop xxh 0 xxh 0 xxh 0 0 ? 1 pac1710/20 ds20005386b-page 22 ? 2015-2016 microchip technology inc. 5.3.2 block read the block read is used to read multiple data bytes from a group of contiguous registers, as shown in table 5-9 . table 5-9: block read protocol start slave address wr ack register address ack start slave address rd ack register data 1 ?? 0 yyyy_yyy 0 0 xxh 0 1 ?? 0 yyyy_yyy 1 0 xxh ack register data ack register data ack register data ack ... register data nack stop 0 xxh 0 xxh 0 xxh 0 ... xxh 1 0 ? 1 ? 2015-2016 microchip technology inc. ds20005386b-page 23 pac1710/20 6.0 registers in hexadecimal order the registers shown in ta b l e 6 - 1 are accessible through the smbus. in the individual register tables that follow, an entry of ? ? ? indicates that the bit is not used and will always read ? 0 ?. table 6-1: register set in hexadecimal order register address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 default value 00h configuration ? cden mskal c2ids c2vds tout c1ids c1vds 00h 01h conversion rate ? ? ? ? ? ? conv1 conv0 03h 02h one-shot os7 os6 os5 os4 os3 os2 os1 os0 00h 03h channel mask register ? ? ? ? c2vs c2vsr c1vs c1vsr 00h 04h high-limit status cvdn ? ? ? c2vsh c2vrh c1vsh c1vrh 00h 05h low-limit status ? ? ? ? c2vsl c2vrl c1vsl c1vrl 00h 0ah v source sampling configuration c2rs1 c2rs0 c2ra1 c2ra0 c1rs1 c1rs0 c1ra1 c1ra0 88h 0bh ch1 v sense sampling configuration ? c1ss2 c1ss1 c1ss0 c1sa1 c1 sa0 c1sr1 c1sr0 53h 0ch ch2 v sense sampling configuration ? c2ss2 c2ss1 c2ss0 c2sa1 c2 sa0 c2sr1 c2sr0 53h 0dh ch1 sense voltage high byte c1sr11 c1sr10 c1sr9 c1sr8 c1sr7 c1sr6 c1sr5 c1sr4 00h 0eh ch1 sense voltage low byte c1sr3 c1sr2 c1sr1 c1sr0 ? ? ? ? 00h 0fh ch2 sense voltage high byte c2sr11 c2sr10 c2sr9 c2sr8 c2sr7 c2sr6 c2sr5 c2sr4 00h 10h ch2 sense voltage low byte c2sr3 c2sr2 c2sr1 c2sr0 ? ? ? ? 00h 11 ch1 v source voltage high byte c1vr10 c1vr9 c1vr8 c1vr7 c1vr6 c1vr5 c1vr4 c1vr3 00h 12 ch1 v source voltage low byte c1vr2 c1vr1 c1vr0 ? ? ? ? ? 00h 13h ch2 v source voltage high byte c2vr10 c1vr9 c2vr8 c2vr7 c2vr6 c2vr5 c2vr4 c2vr3 00h 14h ch2 v source voltage low byte c2vr2 c2vr1 c2vr0 ? ? ? ? ? 00h pac1710/20 ds20005386b-page 24 ? 2015-2016 microchip technology inc. 15h ch1 power ratio high byte c1p15 c1p14 c1p13 c1p12 c1p11 c1p10 c1p8 c1p7 00h 16h ch1 power ratio low byte c1p7 c1p6 c1p5 c1p4 c1p3 c1p2 c1p1 c1p0 00h 17h ch2 power ratio high byte c2p15 c2p14 c2p13 c2p12 c2p11 c2p10 c2p8 c2p7 00h 18h ch2 power ratio low byte c2p7 c2p6 c2p5 c2p4 c2p3 c2p2 c2p1 c2p0 00h 19h ch1 sense voltage high limit c1sh7 c1sh6 c1sh5 c1sh4 c1sh3 c1sh2 c1sh1 c1sh0 7fh 1ah ch2 sense voltage high limit c2sh7 c2sh6 c2sh5 c2sh4 c2sh3 c2sh2 c2sh1 c2sh0 7fh 1bh ch1 sense voltage low limit c1sl7 c1sl6 c1sl5 c1sl4 c1sl3 c1sl2 c1sl1 c1sl0 80h 1ch ch2 sense voltage low limit c2sl7 c2sl6 c2sl5 c2sl4 c2sl3 c2sl2 c2sl1 c2sl0 80h 1dh ch1 v source voltage high limit c1vh7 c1vh6 c1vh5 c1vh4 c1vh3 c1vh2 c1vh1 c1vh0 ffh 1eh ch2 v source voltage high limit c2vh7 c2vh6 c2vh5 c2vh4 c2vh3 c2vh2 c2vh1 c2vh0 ffh 1fh ch1 v source voltage low limit c1vl7 c1vl6 c1vl5 c1vl4 c1vl3 c1vl2 c1vl1 c1vl0 00h 20h ch2 v source voltage low limit c2vl7 c2vl6 c2vl5 c2vl4 c2vl3 c2vl2 c2vl1 c2vl0 00h fdh product id pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 57h/58h feh manufacturer id mid7 mid6 mid5 mid4 mid3 mid2 mid1 mid0 5dh ffh revision rev7 rev6 rev5 rev4 rev3 rev2 rev1 rev0 81h table 6-1: register set in hexadecimal order (continued) register address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 default value ? 2015-2016 microchip technology inc. ds20005386b-page 25 pac1710/20 6.1 read multiple data bytes when any measurement high-byte register is read (v source or v sense ), the corresponding low byte is copied into an internal ?shadow? register. the user is free to read the low byte at any time and be guaranteed that it will correspond to the previously read high byte. regardless if the low byte is read or not, reading from the same high byte register again will automatically refresh this stored low byte data. 6.2 detailed register description register 6-1: co nfiguration register (address 00h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? cden mskal c2ids c2vds tout c1ids c1vds bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7 unimplemented: read as ? 0 ? bit 6 cden : enables the alert pin to be asserted when the conversion cycle is finished. 1 = alert pin will be asserted for 5 s when the conversion cycle is finished. 0 = alert pin is not masked. if any of the appropriate status bits are set, the alert pin will be asserted. bit 5 mskal : masks the alert pin from asserting due to out-of-limit conditions. 1 = alert pin is masked. it will not be asserted for any interrupt condition. the status registers will be updated normally. 0 = alert pin is not masked. it will be asserted for any interrupt condition not masked by register 6-4 . the status registers will be updated normally. bit 4 c2ids : disables the v sense measurement for channel 2 (pac1720) 1 = the device is not measuring the sense voltage. it will update ch2 sense voltage registers when a one-shot command is given. 0 = the device is measuring sense voltage for ch2 unimplemented: read as ? 0 ? (pac1710) bit 3 c2vds : disables the v source measurement for channel 2 (pac1720) 1 = the device is not measuring the source voltage. it will update ch2 source voltage registers when a one-shot command is given. 0 = the device is measuring source voltage for ch2 unimplemented: read as ? 0 ? (pac1710) bit 2 tout : enables the time-out and idle reset functionality of the communications protocol (see section 5.0.5 ?smbus timeout? ). 1 = time out enabled 0 = time out disabled bit 1 c1ids : disables the v sense measurement for channel 1 1 = the device is not measuring the sense voltage. it will update ch1 sense voltage registers when a one-shot command is given. 0 = the device is measuring sense voltage for ch1 bit 0 c1vds : disables the v source measurement for channel 1 1 = the device is not measuring the source voltage. it will update ch1 source voltage registers when a one-shot command is given. 0 = the device is measuring source voltage for ch1 pac1710/20 ds20005386b-page 26 ? 2015-2016 microchip technology inc. register 6-2: conversion rate register (address 01h) u-0 u-0 u-0 u-0 u-0 u-0 r/w-1 r/w-1 ? ? ? ? ? ?conv<1:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-2 unimplemented : read as ? 0 ? bit 1-0 conv<1:0> : determines the conversion rate as shown in table 4-1 . 00b = 1 sample/second 01b = 2 samples/second 01b = 4 samples/second 11b = continuous register 6-3: one-shot register (address 02h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 os<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 os<7:0> : when the device is in the standby state, writing to the one-shot register will initiate a conversion cycle and update all measurements. register 6-4: channel mask register (address 03h) u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? c2vs c2vsr c1vs c1vsr bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-4 unimplemented : read as ? 0 ? bit 3 c2vs : masks the alert pin from asserting when the channel 2 v sense value meets or exceeds the high limit or drops below the low limit (pac1720). 1 = the channel 2 v sense voltage measurement cannot cause the alert pin to be asserted (if enabled). 0 = the channel 2 v sense voltage measurement can cause the alert pin to be asserted (if enabled). unimplemented: read as ? 0 ? (pac1710) bit 2 c2vsr : masks the alert pin from asserting when the channel 2 v source value meets or exceeds the high limit or drops below the low limit (pac1720). 1 = the channel 2 v source voltage measurement cannot cause the alert pin to be asserted (if enabled). 0 = the channel 2 v source voltage measurement can cause the alert pin to be asserted (if enabled). unimplemented: read as ? 0 ? (pac1710) ? 2015-2016 microchip technology inc. ds20005386b-page 27 pac1710/20 bit 1 c1vs: masks the alert pin from asserting when the channel 1 v sense value meets or exceeds the high limit or drops below the low limit. 1 = the channel 1 v sense voltage measurement cannot cause the alert pin to be asserted (if enabled). 0 = the channel 1 v sense voltage measurement can cause the alert pin to be asserted (if enabled). bit 0 c1vsr : masks the alert pin from asserting when the channel 1 v source value meets or exceeds the high limit or drops below the low limit. 1 = the channel 1 v source voltage measurement cannot cause the alert pin to be asserted (if enabled). 0 = the channel 1 v source voltage measurement can cause the alert pin to be asserted (if enabled). register 6-5: high-limit st atus register (address 04h) rc-0 u-0 u-0 u-0 rc-0 rc-0 rc-0 rc-0 cvdn ? ? ? c2vsh c2vrh c1vsh c1vrh bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7 cvdn : indicates that the conversion cycle (see section 4.2 ?conversion cycle? ) is complete. this bit is cleared when read. 1 = conversion complete 0 = conversion not complete bit 6-4 unimplemented : read as ? 0 ? bit 3 c2vsh : this bit is set when the channel 2 v sense value meets or exceeds its programmed high limit (pac1720). 1 = the channel 2 v source voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation unimplemented: read as ? 0 ? (pac1710) bit 2 c2vrh : this bit is set when the channel 2 v source value meets or exceeds its programmed high limit (pac1720). 1 = the channel 2 v source voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation unimplemented: read as ? 0 ? (pac1710) bit 1 c1vsh : this bit is set when the channel 1 v sense value meets or exceeds its programmed high limit. 1 = the channel 1 v sense voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation bit 0 c1vrh : this bit is set when the channel 1 v source value meets or exceeds its programmed high limit. 1 = the channel 1 v source voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation register 6-4: channel mask register (address 03h) (continued) pac1710/20 ds20005386b-page 28 ? 2015-2016 microchip technology inc. register 6-6: low-limit status register (address 05h) u-0 u-0 u-0 u-0 rc-0 rc-0 rc-0 rc-0 ? ? ? ? c2vsl c2vrl c1vsl c1vrl bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-4 unimplemented : read as ? 0 ? bit 3 c2vsl : this bit is set when the channel 2 v sense falls below its programmed low limit (pac1720) 1 = the channel 2 v sense voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation unimplemented: read as ? 0 ? (pac1710) bit 2 c2vrl : this bit is set when the channel 2 v source value falls below its programmed low limit. 1 = the channel 2 v source voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation unimplemented: read as ? 0 ? (pac1710) bit 1 c1vsl : this bit is set when the channel 1 v sense value falls below its programmed low limit. 1 = the channel 1 v sense voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation bit 0 c1vrl : this bit is set when the channel 1 v source value falls below its programmed low limit. 1 = the channel 1 v source voltage measurement caused the alert pin to be asserted (if enabled). 0 = normal operation register 6-7: v source sampling configuratio n register (address 0ah) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2rs<1:0> c2ra<1:0> c1rs<1:0> c1ra<1:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-6 c2rs<1:0> : determines the channel 2 v source measurement sample time, as shown in table 4-2 (pac1720). this will affect the resolution of the data presented in the v source voltage registers. unimplemented: read as ? 0 ? (pac1710) bit 5-4 c2ra<1:0> : controls the digital averaging that is applied to the channel 2 v source measurement, as shown in ta b l e 4 - 3 (pac1720). this determines the number of consecutive samples that are averaged. unimplemented: read as ? 0 ? (pac1710) bit 3-2 c1rs<1:0> : determines the channel 1 v source measurement sample time, as shown in table 4-2 . this will affect the resolution of the data presented in the v source voltage registers. bit 1-0 c1ra<1:0> : controls the digital averaging that is applied to the channel 1 v source measurement, as shown in ta b l e 4 - 3 . this determines the number of consecutive samples that are averaged. ? 2015-2016 microchip technology inc. ds20005386b-page 29 pac1710/20 register 6-8: channel 1 v sense sampling configuration register (address 0bh) r/w-0 r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 ? c1css<2:0> c1sa<1:0> c1sr<1:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7 unimplemented : read as ? 0 ? bit 6-4 c1css<2:0> : determines the channel 1 v sense voltage measurement sample time, as shown in tab l e 4 - 5 . this will affect the resolution of the data in the ch1 sense voltage registers. bit 3-2 c1sa<1:0> : controls the digital averaging that is applied to the channel 1 v sense measurement, as shown in ta b l e 4 - 4 . this determines the number of consecutive samples that are averaged. bit 1-0 c1sr<1:0> : determines the current sense full scale range for channel 1 v sense measurement as shown in ta b l e 4 - 6 . register 6-9: channel 2 v sense sampling configuration register (address 0ch) r/w-0 r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 r/w-1 r/w-1 ? c2css<2:0> c2sa<1:0> c2sr<1:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7 unimplemented : read as ? 0 ? bit 6-4 c2css<2:0> : determines the channel 2 v sense voltage measurement sample time, as shown in tab l e 4 - 5 (pac1720). this will affect the resolution of the data in the ch2 sense voltage registers. unimplemented: read as ?0?(pac1710). bit 3-2 c2sa<1:0> : controls the digital averaging that is applied to the channel 2 v sense measurement, as shown in ta b l e 4 - 4 (pac1720). this determines the number of consecutive samples that are averaged. unimplemented: read as ? 0 ? (pac1710) bit 1-0 c2sr<1:0> : determines the channel 2 current sense full scale range channel 2 v sense measurement as shown in tab l e 4 - 6 (pac1720). unimplemented: read as ? 0 ? (pac1710) pac1710/20 ds20005386b-page 30 ? 2015-2016 microchip technology inc. register 6-10: channel 1 v sense result register (addresses 0dh and 0eh) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c1sr<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 u-0 u-0 u-0 u-0 c1sr<7:4> ? ? ? ? bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 15-4 c1sr<15:4> : these registers contain the most recent digitized value channel 1 v sense samples. bit 3-0 unimplemented : read as ? 0 ? register 6-11: channel 2 v sense result register (addresses 0fh and 10h) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c2sr<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 u-0 u-0 u-0 u-0 c2sr<7:4> ? ? ? ? bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as 0 -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 15-4 c2sr<15:4> : these registers contain the most recent digitized value channel 2 v sense samples (pac1720). unimplemented: read as ? 0 ? (pac1710) bit 3-0 unimplemented : read as ? 0 ? ? 2015-2016 microchip technology inc. ds20005386b-page 31 pac1710/20 register 6-12: channel 1 vsource result register (addresses 11h and 12h) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c1vr<15:8> bit 15 bit 8 r-0 r-0 r-0 u u-0 u-0 u-0 u-0 c1vr<7:5> ? ? ? ? ? bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 15-5 c1vr<15:5> : these registers contain the most recent digitized value channel 1 v source samples. 400h = 20v 200h = 10v 100h = 5v 080h = 2.5v 040h = 1.25v 020h = 625 mv 010h = 312.5 mv 008h = 156.25 mv 004h = 78.125 mv 002h = 39.063 mv 001h = 19.531 mv bit 4-0 unimplemented : read as ? 0 ? pac1710/20 ds20005386b-page 32 ? 2015-2016 microchip technology inc. register 6-13: channel 2 vsource result register (addresses 13h and 14h) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c2vr<15:8> bit 15 bit 8 r-0 r-0 r-0 u-0 u-0 u-0 u-0 u-0 c2vr<7:5> ? ? ? ? ? bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 15-5 c2vr<10:0> : these registers contain the most recent digitized value channel 2 v source samples (pac1720). 400h = 20v 200h = 10v 100h = 5v 080h = 2.5v 040h = 1.25v 020h = 625 mv 010h = 312.5 mv 008h = 156.25 mv 004h = 78.125 mv 002h = 39.063 mv 001h = 19.531 mv unimplemented: read as ? 0 ? (pac1710) bit 4-0 unimplemented : read as ? 0 ? register 6-14: channel 1 power ratio register (addresses 15h and 16h) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c1p<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c1p<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 15-0 c1p<15:0> : these registers contain the most recent channel 1 power ratio calculations. this is a 16-bit binary number representing a ratio based on power fsr. ? 2015-2016 microchip technology inc. ds20005386b-page 33 pac1710/20 register 6-15: channel 2 power ratio register (address 17h and 18h) r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c2p<15:8> bit 15 bit 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 c2p<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 15-0 c2p<15:0> : these registers contain the most recent channel 2 power ratio calculations (pac1720). this is a 16-bit binary number representing a ratio based on power fsr unimplemented: read as ? 0 ? (pac1710) register 6-16: channel 1 v sense high limit register (address 19h) r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c1sh<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c1sh<7:0> : two?s complement high-limit channel 1 v sense 0100_000 = 1024 0010_0000 = 512 0001_0000 = 256 0000_1000 = 128 0000_0100 = 64 0000_0010 = 32 0000_0001 = 16 1111_1111 = -1 1000_000 = -1024 pac1710/20 ds20005386b-page 34 ? 2015-2016 microchip technology inc. register 6-17: channel 2 v sense high-limit register (address 1ah) r/w-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c2sh<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c2sh<7:0> : two?s complement high-limit channel 2 v sense (pac1720) 0100_000 = 1024 0010_0000 = 512 0001_0000 = 256 0000_1000 = 128 0000_0100 = 64 0000_0010 = 32 0000_0001 = 16 1111_1111 = -1 1000_000 = -1024 unimplemented: read as ? 0 ? (pac1710) register 6-18: channel 1 v sense low-limit register (address 1bh) r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c1sl<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c1sl<7:0> : two?s complement low-limit channel 1 v sense 0100_000 = 1024 0010_0000 = 512 0001_0000 = 256 0000_1000 = 128 0000_0100 = 64 0000_0010 = 32 0000_0001 = 16 1111_1111 = -1 1000_000 = -1024 ? 2015-2016 microchip technology inc. ds20005386b-page 35 pac1710/20 register 6-19: channel 2 v sense low-limit register (address 1ch) r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2sl<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c2sl<7:0> : two?s complement low-limit channel 2 v sense (pac1720) 0100_000 = 1024 0010_0000 = 512 0001_0000 = 256 0000_1000 = 128 0000_0100 = 64 0000_0010 = 32 0000_0001 = 16 1111_1111 = -1 1000_000 = -1024 unimplemented: read as ? 0 ? (pac1710) register 6-20: channel 1 v source high-limit register (address 1dh) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c1vh<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as 0 -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c1vh<7:0> : two?s complement high-limit channel 1 v source 80h = 20v 40h = 10v 20h = 5v 10h = 2.5v 08h = 1.25v 04h = 625 mv 02h = 312.5 mv 01h = 156.25 mv pac1710/20 ds20005386b-page 36 ? 2015-2016 microchip technology inc. register 6-21: channel 2 v source high-limit register (address 1eh) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 c2vh<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c2vh : two?s complement high-limit channel 2 v source (pac1720) 0h = 20v 40h = 10v 20h = 5v 10h = 2.5v 08h = 1.25v 04h = 625 mv 02h = 312.5 mv 01h = 156.25 mv unimplemented: read as ? 0 ? (pac1710) register 6-22: channel 1 v source low-limit register (address 1fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c1vl<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c1vl<7:0> : two?s complement low-limit channel 1 v source 0h = 20v 40h = 10v 20h = 5v 10h = 2.5v 08h = 1.25v 04h = 625 mv 02h = 312.5 mv 01h = 156.25 mv ? 2015-2016 microchip technology inc. ds20005386b-page 37 pac1710/20 register 6-23: channel 2 v source low-limit register (address 20h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2vl<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 c2vl<7:0> : two?s complement low-limit channel 2 v source 0h = 20v 40h = 10v 20h = 5v 10h = 2.5v 08h = 1.25v 04h = 625 mv 02h = 312.5 mv 01h = 156.25 mv register 6-24: product register (address fdh) r-0 r-1 r-0 r-1 r-0 r-1 r-1 r-1 pid<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 pid<7:0> : product id for pac1710/20 57h = pac1720 58h = pac1710 register 6-25: mchp id register (address feh) r-0 r-1 r-0 r-1 r-1 r1 r-0 r-1 mid<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 mid<7:0> : manufacturer id pac1710/20 ds20005386b-page 38 ? 2015-2016 microchip technology inc. register 6-26: revision register (address ffh) r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 rev<7:0> bit 7 bit 0 legend: r = read bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit in unknown bit 7-0 rev<7:0> : silicon revision ? 2015-2016 microchip technology inc. ds20005386b-page 39 pac1710/20 7.0 package description 7.1 package marking information 10-lead vdfn (3x3x0.9 mm) example part number code PAC1710-1-AIA-TR 25ww pac1720-1-aia-tr 26ww legend: y year code (last digit of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pac1710/20 ds20005386b-page 40 ? 2015-2016 microchip technology inc. b a 0.10 c 0.10 c (datum b) (datum a) c seating plane note 1 12 n 2x top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 12 n 0.10 c 0.05 c microchip technology drawing c04-206 % sheet 1 of 2 10-lead very thin plastic dual flat, no lead package (9q) - 3x3 mm body [vdfn] 2x d e d2 e2 k 10x b e 0.10 c a b 0.05 c a a1 (a3) 10x p l p microchip technology drawi ng c04-206b sheet 1 of 2 ? 2015-2016 microchip technology inc. ds20005386b-page 41 pac1710/20 microchip technology drawing c04-206 % sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height terminal width terminal length terminal thickness pitch standoff units dimension limits a1 a b (a3) e l n 0.50 bsc 0.20 ref 0.35 0.18 0.80 0.00 0.25 0.40 0.85 0.02 millimeters min nom 10 0.45 0.30 0.90 0.05 max k0.30 0.25 - ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad 10-lead very thin plastic dual flat, no lead package (9q) - 3x3 mm body [vdfn] overall width overall length exposed pad width exposed pad length d e2 d2 e 1.50 2.20 3.00 bsc 2.30 1.60 3.00 bsc 1.70 2.40 exposed pad chamfer p - 0.25 - pac1710/20 ds20005386b-page 42 ? 2015-2016 microchip technology inc. recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-2206 % 10-lead very thin plastic dual flat, no lead package (9q) - 3x3 mm body [vdfn] silk screen 1 2 c g1 y1 y2 (g2) x1 10 dimension limits units ch optional center pad width center pad chamfer optional center pad length contact pitch x2 y2 2.40 1.70 millimeters 0.50 bsc min e max 0.28 contact pad length (x10) contact pad width (x10) y1 x1 0.80 0.30 bsc: basic dimension. theoretically exact value shown without tolerances. notes: 1. nom c contact pad spacing 3.00 contact pad to contact pad (x8) g1 0.20 contact pad to center pad (x10) g2 0.25 ref ref: reference dimension, usually without tolerances, for reference only. thermal via diameter v thermal via pitch vx thermal via pitch vy 0.30 1.00 1.00 2x ch vy vx ?v x2 for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 2. dimensioning and tolerancing per asme y14.5m e ? 2015-2016 microchip technology inc. ds20005386b-page 43 pac1710/20 appendix a: revision history revision b (february 2016) the following was modified: 1. updated the package drawings in section 7.0, package description revision a (may 2015) ? replaces previous smsc version 1.1 (12-08-11) ? updated the absolute maximum ratings in section 1.1, electrical specifications ? added information for the dual high-side current sensor (pac1720) revision 1.1 (december 2011) ? initial release pac1710/20 ds20005386b-page 44 ? 2015-2016 microchip technology inc. notes: ? 2015-2016 microchip technology inc. ds20005386b-page 45 pac1710/20 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. -x -xxx -xx tape and package smbus address device device: pac1710/20: high-side power/current monitor with analog output smbus address: -1 = selectable address package: aia = 10-lead 3 mm x 3 mm vdfn shipping pack: tr =4,000 piece tape and reel examples: a) PAC1710-1-AIA-TR: single-channel high-side current monitor 3x3 vdfn 8-lead package, shipped in a 4,000 piece tape and reel reel pac1710/20 ds20005386b-page 46 ? 2015-2016 microchip technology inc. notes: ? 2015-2016 microchip technology inc. ds20005386b-page 47 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015-2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0276-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds20005386b-page 48 ? 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